1. Field of the Invention
The present invention relates to a circuit testing method. In particular, the present invention relates to a testing method for pixel storage capacitance of a thin film transistor display circuit. A reliable and precise testing result of the yield can be obtained in conditions that parasitic capacitance is much larger than a pixel capacitance.
2. Description of the Related Art
The pixels of liquid crystal display (LCD) or organic liquid crystal display (OLED) become more and more, the area of large area display also become larger and larger, the parasitic capacitance Csp of the source line of the thin film transistor would be much more larger than the pixel storage capacitance Cs. The measuring signal is too small in yield testing of quality control step, so that the accuracy is not good enough.
Generally, to measure the yield of the pixel capacitance, it is always to charge the pixel capacitance with a voltage of several volts. However, the parasitic capacitance is also charged simultaneously, and the signal is difficult to separate. A Taiwan patent with application number of 88108530 (publishing number: 473622) from Asia of a Japanese company, title: “A testing method and apparatus for thin film transistor” is an example. Refer to FIG. 1, FIG. 1 is an equivalent circuit for testing pixel capacitance of a prior art, where Cs is the pixel capacitance, Csp is the parasitic capacitance of the source line of the TFT array, and Csp>>Cs, ΔCs is a standard capacitance of known value. S1 is the connection switch of Csp and ΔCs, S2 is the pixel switch transistor. As shown in FIG. 1(a), in the first stage, charging the pixel capacitor Cs to Vp, then switch OFF the pixel switch transistors, then charging the parasitic capacitance to Vs, where Vs≠Vp, in the mean time, the additive capacitor CT, which is in parallel with the pixel capacitor is also charged. Next switch ON S2 during testing, measuring the voltage Va1 of the parallel capacitors Cs∥Csp∥CT. The voltage difference of ΔVs between Va1 and Vs is very small, now ΔVs1=Va1−Vs=Cs/CT*(Vp−Vs), because Va1, Vs, CT and Vp are known, then Cs can be calculated, but the error is large, so that a second stage measurement is required as shown in FIG. 1(b). Set S1 ON to charge Csp, in the mean time, Vs also charge to ΔCs, i.e. charge to Csp∥ΔCs∥CT, where ΔCs is a standard capacitance of known value. Finally, set S2 ON, measuring the voltage Va2 of the parallel capacitors Cs∥Csp∥CT, and ΔVs2=Va2−Vs=Cs/CT*(Vp−Vs), according to the values of ΔVs1 and ΔVs2, the value of Cs can be calculated as follow:Cs=ΔCs*ΔVs1*ΔVs2/{(Vp−Vs)*(ΔVs1−ΔVs2)}
This prior art method needs a two stage measurement, must take a long time, the signal is also too weak, the reliability is not enough and the accuracy is also bad, may not meet the requirement of the industry.
What is needed is an improved testing method satisfied the need of testing small pixel capacitor and still has a stronger signal to increase the accuracy and reliability.
It also need an improved testing method satisfied the need of obtaining a result with one testing step for each pixel capacitor to save time and manpower.